The invention relates generally to circuits that utilize an accelerated graphics protocol (AGP) bus, and more particularly to the method and apparatus for supporting multiple bus masters with the AGP bus.
Computing systems are often constructed from a number of components produced by a number of different manufacturers. In order to aid in the design and production of various components that are capable of interoperating in computing systems, standards are established such that components designed by different manufacturers are capable of operating in a common system. One such example of a portion of the computing system that has been standardized is the accelerated graphics protocol (AGP) bus structure.
The AGP bus is an intercoupling bus that expands on the protocol of the peripheral component interconnect (PCI) bus standard. The AGP expansion of the PCI bus adds additional signals that can be used to allow for specific types of data transfers over the bus structure that may be more efficient than what was possible in the original PCI protocol. The PCI bus protocol is detailed in the PCI local bus specification, and the AGP enhancement of the PCI bus protocol is described in the AGP specification R2.0.
The AGP bus is typically used in video graphics circuits to allow a device such as a graphics processor to couple to a bus interface. The bus interface enables the graphics processor to communicate with other components of the computing system. The AGP bus consists of a number of signals that carry control and data information to and from the end components coupled to the AGP bus. In order to promote efficient data transmission using the AGP bus, one of the components coupled to the bus typically becomes a bus master, which allows for data to be transmitted in a manner which is more efficient than transfers that do not using bus mastering.
As graphics systems continue to evolve, the complexity of the graphics processing operation increases dramatically. As such, it may be desirable to include multiple graphics processors on a single graphics processing circuit, such as a graphics card that would be inserted into a personal computer. Such circuits typically are only provided with a single interface to a single AGP bus structure, and therefore the multiple graphics processors must share the capabilities of the AGP bus in their interaction with other computing system components.
Therefore, a need exists for a method and apparatus that allows multiple bus masters to be supported on a single AGP bus structure.